A sense amplifier generally senses the value of a bit stored in a memory cell of a RAM (random access memory) integrated circuit. Sense amplifier performance has a significant effect on memory access time and power use, consequently they are relatively critical circuits in the periphery of RAM devices. Most memory input/output (IO) circuits consist of a sense amplifier followed by a latch. If the memory is pipelined then this output latch is followed by at least another latch, if not a full flip-flop circuit. FIG. 1A is a circuit diagram of a memory circuit with a sense amplifier as known in the prior art. Circuit 100 includes a memory cell 106, pre-charge circuit 106, isolation circuit 104, and sense amplifier 102. Circuit 100 represents a cross-section of the read data path for a single column for a typical RAM memory array. Sense amplifier 102 examines the bit line 101 to determine whether a logic 1 or logic 0 is stored in cell 106. The sense amplifier 102 is activated when the Set Sense Amp (SSA) signal 103 goes high. Proper timing of the SSA signal is critical as it is used to determine when the data on the bit lines is sensed. Incorrect timing of this signal can lead to memory errors even when the correct binary value may be stored in the cell 106. For implementation within a multi-cell memory array, each sense amplifier is followed by one or more latch or flip-flop circuits (not shown).
Many memory devices feature scannable IO to facilitate boundary scan testing in which interconnects and memory circuits are tested without the use of physical test probes. Test cells are connected to each pin of a memory device to selectively override the functionality of that pin. The boundary scan latch cells are configured so that in normal mode, they have no effect on circuit operation, and in test mode, they enable a data stream to be passed from one latch to the next. For scannable IO, any output latch or flip-flop circuit must also be scannable.
Scannable IO circuits are used extensively in pseudo-dual port (pdp) memory architectures in which the memory array is accessed twice within the same cycle using a memory precharge—data transfer cycle. FIG. 1B illustrates a known memory access cycle for a typical pdp memory device. For a single cycle of the clock signal 122, the memory is accessed in a Read/Precharge/Write/Precharge sequence 124. The sense amplifier circuit is activated at the end of the read cycle and has the read data, 126, and at some point before the end of the clock cycle, the data is stored in a latch, 128. For a pipelined memory, the data should be output from the memory at the end of the clock cycle 122. However, for the timing shown in FIG. 1B, it is not possible to hold the data in the sense amplifier until that time, because of the need to precharge the sense amplifier in preparation for the next read. The precharge cycle puts the bits in a state where they can be read. This requires the use of an output latch to store the data prior to a new read cycle, 110. This results in the need for three storage elements, the sense amplifier, the first latch 128 and the second latch (output) 130 connected to the output pin. The sense amplifier holds the valid data from the point where it is successfully sensed, until it is precharged. The first latch holds the data until some time after the data is sensed after the clock edge, and the second latch holds the data from edge to edge. In many current scannable memory 10 circuits, the output latch is a conventional multiplexed flip-flop circuit. Alternative known circuits may employ a dual flip-flop in place of the output latch, in which case the scan circuit comprises a sense amplifier and three latches. Such circuits add significant complexity to the memory 10 stage and can take up significant chip space in the finished integrated circuit (IC) device.
Significant space on memory IC's can also be taken up by circuitry that facilitates in-circuit or self-testing of memory devices. Current systems that perform built-in self-test (BIST) functionality generally implement area intensive parallel tests that can consume significant die area in memory IC's.